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  • LDOs are linear regulators and therefore their efficiency is lower than switching regulators.

  • To get the most out of your LDO application

  • the LDO power dissipation needs to be carefully considered

  • So let’s examine LDO power dissipation in more detail.

  • When choosing an LDO

  • the maximum LDO input voltage range and LDO current capability are important factors to consider.

  • But, larger current or larger voltage drop across the LDO

  • quickly leads to higher device power dissipation

  • This plot shows the relation between LDO power dissipation, LDO voltage drop and LDO current

  • When power dissipation increases,

  • The LDO package needs to be able to handle this power dissipation.

  • The power dissipation in the LDO is determined by the voltage drop across the LDO

  • multiplied by the current passing through the LDO.

  • This power is dissipated in the LDO pass element, which heats the silicon die.

  • But how much power can you actually dissipate in the LDO?

  • This depends on the IC package, the PCB layout and the ambient temperature.

  • Let’s have a look at some examples.

  • Here is a drawing of the small SOT23 package in a normal layout.

  • When you look inside the package you can see that the center pin is connected to the die mounting lead frame.

  • The silicon die is mounted underneath on this center pin lead frame.

  • When the silicon die is becoming hot

  • this heat will be transferred to several parts of the package:

  • Some heat goes through the plastic directly to the ambient.

  • Some heat goes through the pins to the PCB copper and then to the ambient.

  • Due to the thin bonding wires

  • he outer pins do not have a good thermal connection with the silicon die,

  • and their heat transfer to the PCB is limited

  • The center ground pin has a good thermal connection to the silicon die

  • so more heat is transferred via this pin

  • To improve the cooling capabilities of this package

  • it is important to add some extra copper to the pins

  • especially to the center ground pin

  • With improved layout, more power can be dissipated without overheating the silicon die

  • Here is a different IC package: the popular SOP-8 package with exposed pad.

  • In this package, the silicon die is mounted on a separate copper pad

  • which has an exposed surface at the bottom of the package

  • In the PCB layout

  • this exposed pad should always be connected to a copper area underneath the IC

  • When the die gets hot

  • some heat will flow through the plastic package and some heat will flow through the pins.

  • However, the majority of heat will flow through the exposed pad,

  • provided there is enough PCB copper connected to it

  • It is therefore important to connect sufficient copper to the exposed pad,

  • to allow more heat flow via this route

  • When you use a multi-layer PCB,

  • you can add several vias under the exposed pad which can connect to the PCB inner layers

  • These will act as effective heat sinks

  • and allows you to dissipate more power in this package.

  • So how much power can you dissipate in each package?

  • You can calculate the allowed power dissipation by dividing the allowed temperature difference

  • between junction and ambient by the thermal resistance between junction and ambient.

  • The thermal resistance value - theta junction amaient is shown in the datasheet,

  • but keep in mind that this value is based on the JEDEC method

  • which can be a bit conservative

  • Here are some practical power dissipation limits for various package types

  • based on a normal PCB layout

  • with some extra copper connected to the package pins and thermal pad

  • a maximum PCB ambient temperature of 60℃

  • and a maximum silicon die temperature of 125 ℃

  • If your ambient temperature is lower

  • the power dissipation can be higher.

  • If your PCB is small, or there are other hot components nearby

  • the maximum power dissipation may be less

  • I hope you now have a better understanding

  • about power dissipation and thermal condistions to LDOs

  • For more information on Richtek LDOs,

  • Please click the link at the left side,

  • or visit Richtek websit at:


LDOs are linear regulators and therefore their efficiency is lower than switching regulators.


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B2 中上級

LDOの消費電力 (LDO Power Dissipation)

  • 305 24
    jmkuoa に公開 2021 年 01 月 14 日