字幕表 動画を再生する 英語字幕をプリント In the last video we built a JK flip-flop that didn't work all that well with we use an RC circuit to detect the rising edge of the clock but because the JK flip-flop toggled so quickly we encountered this racing phenomenon where we toggle many times for each clock pulse and we found it was really difficult to fix you know almost impossible to fix on the breadboard to get that clock pulse to be so short you know the pulse that we're generating the RC circuits from the rising edge of the clock to get that to be so short that was only toggle once we found out was it almost impossible to to get that working for bus the on the breadboard so what can we do well there's another way to build a JK flip-flop and that's this circuit here which is called a master-slave JK flip-flop and so what you'll see if you look at this is you see there to essentially 2 SR latches built into this, there is one here and then one here and you can think of this is having you know you're you're set in your reset and this case will be the Q compliments and this will be the Q output and then over here you know this will be the reset and the set and this is our Q output in our compliments Q. So these are two SR latches which you know you can look at my previous video on those, but then outside of that you have these AND gates that are essentially gating the clock or gating the SR latches based on the clock so for the moment let's, let's ignore the feedbacks we'll get to that in a minute but if you look at just these two inputs of the AND gate the J input and the clock or in this case the K input and the clock basically we're saying is we're saying this SR latch is not going to be active unless the clock is high when the clock is high then you know J will pass through and set or K will pass through and reset anytime the clock is high So this is just sort of like a you know an SR latch with an Enable you want to think of the clock in that way and then same thing if you look at that the slave over here and on the salve side you've got an SR latch as well, the inputs are coming from the master but then instead of the clock input coming into the AND gates you've got the inverted clock input and so the slave is only going to be active when the clock is low and so the interesting piece of this is that you're never going to have a situation where both of these SR latches are active at the same time because the clock is either going to be high which case this was active or the clock is going to be low which case this one is active and so if you want to step this this flip-flop you want to get the Q output to be high then you know you bring J high and then you toggle the clock high and low and so with J high when the clock goes high then it's going to set the first latch and so the Q output of that first latch is going to go high then when the clock goes low that enables the second latch and that Q output gets fed through and sets the second latch which causes this Q output to go high so you can see setting the J input toggling the clock high then low causes the Q to get set and then the same way with K if you set K high and then you toggle the clock high then low that it resets this latch and then the clock goes low and reset this latch which resets the output so it sets Q to 0 so effectively kind of a two-step process with the clock has to go high then low now what about that JK flip-flop so we should have that property where J&K are both high than the output should toggle each time the clock pulses so in that case when J & K are both high when the clock goes high the first latch is either going to set or reset depending on what the current output is so the current output is that Q is high then he's gonna come out here and this the AND gate is going to turn on its going to reset but if the current output is low and then a compliment output is high then this is going to come around at the top AND gate is going to turn on its going to set so essentially this first latch will output on this Q the opposite of whatever currently being output over here if both JK are set and the clock is high but its fine if the clock stays high because the second latch is not going to be enabled the clock is high then when we invert it this is going to be a LOW these AND gates are going to be off this latch is not going to be active and so this output will stay stable so it doesn't matter if the clock state high for for whatever period of time the first latch will switch but the second one won't until the clock goes low once the clock goes low then that second latch enables and the output of the first latch gets fed into the second latch so whether that was setting it or resetting it and then when that second latch either sets or resets that's when the final output changes and of course at that point the output changes it doesn't matter what's getting fed into the first stage over here because your clock is low at this point and so these AND gates you both going to be OFF so nothing is going to change here So this circuit essentially has the exact same behavior as the first circuit that we're looking at except we don't have this issue of of trying to make sure this pulse is so narrow that we don't have this racing where you know the outlet toggles and then a toggles again and toggles again toggles again over and over because we're not we're not trying to use it on RC circuits to create a pulse out of our clock where you know using the fact that the clock goes high to set one latch and when the clock goes low to set the next latch based on the first latch in that way our feedback you know can't get back around to the input until you have a full clock cycle and so this way this will only toggle once per clock cycle and we don't have to deal with any of the you know really stringent timing requirements you know where we're looking at this you know 40 milliseconds propagation time and so forth so go ahead built the this circuit master-slave JK flip-flop and just like last time i've got two inputs here this is our J&K input and again they're you know tide low to this pulldown resistor but then when you push the button that goes high. So those two inputs go into this is again are our three input AND gates so both of the input go into those 2 AND gates and then this this white wire is connecting our clock and so will connect our clock into that and then of course with the third input is the feedback that comes back around that these two green wires here and the output of these AND gates are the two blue wires to go up to our to our first two NOR gates which are the top two NOR gates on this says 74LS02 and then you know the outputs with other connected back to the inputs you too yellow wires in the outputs of those come to these first two LEDs so you two LEDs here give us that you know a way to see what's going on at this point here so this is our you know our Q compliment for the first stage and this is our Q for the first stage then those outputs go over here to another to another I guess that this is a 74LS08 it's a two input AND gates and also connected to to those AND gates is our clock except this time the clock is coming so this is original clock it's going over to 74LS04 inverter and they're coming out of that inverter and going into the AND gates here and then the outputs of AND gates go back to our 74LS02 are NOR gates and here we are using the bottom two NOR gates for these and so that is yeah that's these blue wires the wires are .. , No the blue wires are here coming out of our AND gate going into our NOR gates right that's those two blue wires and then of course we've got these two yellow wires 2 short yellow wires are the cross overs here between our inputs outputs and the NOR gates and then the outputs and NOR gates that these two yellow wires that go over to our two LEDs so this is our Q our final Q output and this is our Q complement the output so let's hook it up to Power and see what happens I'm gonna hook into power our clock and got running over here and so the first thing you see is of course looks like Q compliment is on on our first stage and then of course Q complement is on on our second stage and if I hook a clock up here OK nothing happens but i should be able to set and reset it so I hit J that should set it so Q should go high and in fact it does of course you see Q goes high first on our first stage and then on our second stage and then if I reset it it resets. The other thing that I'll show you is like put our clock into manual mode so here I can just manually activate the clock that way what you'll see if I go ahead and try to see if I set thi so I turn on the J input , and of course nothing's happening to the clock not doing anything when the clock goes high you see the first stage changes and then it's when the clock goes low the second state changes and now you know I set the output by inputting a 1 to our J input and toggling clock high then low so there's a JK flip-flop it should toggle so if i get a 1 both inputs and actually just let the clock run you see with each clock pulse each time the clock goes high the first one toggle each time the clock goes low the second one toggles and so if you just look at the bottom-left LED that's our Q output of our flip-flops and you see it's just going high-low high-low it's toggling which is exactly what we'd expect and of course because we don't have any of the you know crazy timing requirements here this is going to work very consistently not gonna have any of the you know flakiness issues that I was having with with the JK flip-flop that was using his RC circuit to try to detect the rising edge of the clock and in fact because it's much more reliable this is this master slave arrangement for building a JK flip-flop is typically the way that JK flip-flops are built-in in practice. So now that you understand how the JK flip-flop works in future videos rather than building you know JK flip-flop from all these components we go ahead and use a prepackaged JK flip-flop in this case 74LS76 which is a dual master slave JK flip-flop it's got 2 you know that's what makes it a duel is two of them and course master slave JK flip-flop you you know what that means that's what we just talked about and so if you look at at the flip-flop here you see it's got you know course the J input and the K here it is the K input and the wire goes all the way around there but you've got your J input your K input your Q output your complimentary Q outputs that's what it means complimentary output as both Q and the inverted Q outputs and this will also has a Preset in a Clear and so the preset and clear are these two other inputs that basically just force it to either set or reset so rather than it kind of bypasses the clocking mechanism to you can just force it to reset reset those kinda another little feature that these have and then the other thing is the clock input here is says its inverted it has a little bubble here and that's actually absolutely correct because this is a master-slave JK flip-flop and you remember that the out the final output the Q output doesn't actually change until the clock you know both goes high and then goes low and so unlike the first JK flip-flop that we we tried to build the triggers on the rising edge of the clock the master-slave JK flip-flop because it requires the clock to go high and then low again the output triggers on the falling edge of the clock and so that's indicated in a in a symbol for it with this little bubble here showing that this is a you know this clock input is looking at the falling edge with that bubble means. So the next video we'll will hook a couple of the 74 and 76's together and build a binary counter
B1 中級 マスタースレーブJKフリップフロップ (Master-slave JK flip-flop) 4 0 林宜悉 に公開 2021 年 01 月 14 日 シェア シェア 保存 報告 動画の中の単語