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  • >> Jim Pytel: Good day.

  • This is Jim Pytel from Columbia Gorge Community College.

  • This is Digital Electronics.

  • This lecture is entitled Digital Analog Conversion Methods R2R

  • Ladder Method.

  • In our last discussion about digital to analog conversion,

  • we made use of binary weighted input circuit

  • which I have drawn right here.

  • As easy as it was to understand the binary weighted input

  • circuit, there becomes a problem with it

  • because notice those resistors.

  • R2R, 4R, 8R.

  • They're not exactly the most scalable methods.

  • For example, if I wanted to expand this to a fifth position,

  • D4 would R, D3 would have 2R.

  • D2 would have 4R, D1 would have 8R.

  • D0 would have 16R.

  • So for me to expand the pit position,

  • I have to do some fundamental change of those inputs.

  • Additionally, think about the manufacturer ability

  • of all these things.

  • Are resistors of those values even commercially available?

  • Is there an 8R value?

  • Is there a 16R value?

  • Is there 32 128 times that?

  • So if the picture if your using a huge selection of resistors

  • to actually perform this.

  • Compare and contrast to what we were just about to discuss here.

  • The R2R Ladder Method.

  • I'm discussing this circuit right here,

  • you can optionally take out the resistive ladder and feed it

  • into an amplifier, which we'll talk about in a little bit here.

  • But an R2R2 does not necessarily need that amplifier right now.

  • As confusing as this circuit may look here,

  • notice I'm only using two values,

  • namely R as the name implies, 2R.

  • Additionally notice the functional units

  • that these things are composed of.

  • Look at this repetitive 2R, R, L shade.

  • 2RR, 2RR. The only difference being this 2R2R at the very end.

  • It stands to conjecture that if I wanted to perhaps expand

  • to a fourth bit position, all I would have to do is put

  • in that 2RR sixth bit position, so on and so forth.

  • You're expanding those functional blocks using the same

  • resistive values and that's exactly how it happens.

  • The binary weighted method here,

  • basically how we did this was the lowest significant bit

  • contributed less.

  • The most significant bit contributed more.

  • Exact same thing for the resistive ladder network here.

  • How we do that though is kind of different.

  • It's through this voltage division.

  • Notice my output voltage is right there and for D0

  • to contribute anything, it's got to go through one stage,

  • two stage, three stage,

  • four stages to the get to that output.

  • And each time it's successfully being divided.

  • And notice how I've heard D3 only has go to through one stage

  • of voltage division for it to do so.

  • And the reason why I'm saying it's optional

  • to put an amplifier there at the end is this circuit will perform

  • and there will be a single analog voltage of we put

  • in a parallel binary value.

  • However, it's limited to that range of that logic load.

  • If we wanted to somehow step it up and down or perhaps we want

  • to amplify or attenuate it, we could use operational amplifier

  • at the very end and adjust the gain with its feedback resistor.

  • So let's go ahead and perform a quick analysis

  • on the R2R Ladder Network

  • and what you'll find is you can be making use of evidence there.

  • So I know [Inaudible] you're going to have to use some

  • of your basic understands of electronics to understand this.

  • It's not that hard though

  • because of its repetitive functional unit nature.

  • Namely this 2RR combination and what you try

  • to do is just basically take your basic resistive network

  • and give it these divisions right there, right there

  • and another one right there.

  • What does [Inaudible] states is basically I can take the open

  • circuit voltage and the resistance

  • with the voltage source removed, and replace it

  • with the voltage equivalent and a resistor in series.

  • So what we can do is kind of analyze each stage

  • and see what contributes there.

  • So for example, D0.

  • Think about it from the perspective of D0

  • and all I've done between this top diagram here is all I did

  • was shift that one down every so slowly.

  • From the perspective of D0, it is being voltage divided

  • between two identical resistances, 2R, 2R.

  • Say for example, D0 was a logical value of five volts.

  • What's the open circuit voltage there?

  • Well it should be five volts divided by two and a half volts.

  • So we've already performed the division of that.

  • What is the Thevenin equivalent resistance at that point

  • where we remove that source and what you get is basically 2Rs

  • in parallel, which is the single R-value here.

  • And notice what it's setting us up for.

  • It's setting us up for 2Rs in series.

  • What is 2Rs in series?

  • Well it's 2R.

  • And if we were to form, again, a Thevenin's equivalent,

  • we're going to have 2R in parallel with 2R.

  • So that's our first [Inaudible] 2Rs in series to get this guy

  • and then we got 2Rs in parallel to get and R,

  • this R. 2Rs in series make, you guessed it, 2R in parallel.

  • You get the picture here is basically we're performing this

  • repetitive analysis over and over.

  • Ultimately what we can get is basically the Thevenin's

  • equivalent resistance for the whole network is R,

  • regardless of how many stages you've gone through there.

  • So this could potentially simplify all your filtration

  • for any stage of your circuits [Inaudible] R,

  • regardless of the number of the bits.

  • And along the way, we could have been doing

  • that Thevenin's equivalent open circuit voltage

  • for the contribution in this particular case of D0.

  • But what happens is basically we saw in the first stage,

  • you got to reduce by half.

  • What's going to happen in the second stage?

  • Half again.

  • Third stage, half again.

  • Fourth stage, half again.

  • What do we got here?

  • Basically the output voltage is D0 divided by 16.

  • You get the picture.

  • It's contributing a sixteenth of it.

  • And we do the same thing for D1 or it's an eighth.

  • D2, a fourth and finally, D3, a half.

  • And in the case of a five-volt TTL system,

  • basically the D0 bit can contribute .3125 volts.

  • D1 can contribute .625 volts.

  • D2 can contribute 1.25 volts.

  • D3 can contribute 2.5 volts.

  • Basically our final range should be 4.6875 volts

  • and the reason why it's shy of five volts is because think

  • about it, we are using 16-bit positions to represent

  • that range there, one of which quadruple zero is being

  • to represent zero.

  • So that's basically we can represent this in steps

  • of a sixteenth of five volts, which is .3125, our LSB.

  • So that's our minimum resolution right there.

  • In the case where we wanted to go ahead and amplify this thing,

  • that's when that output stage, V0, is being fed

  • into this operational amplifier

  • on the lower right hand corner there to potentially expand

  • that range to a higher voltage

  • or perhaps attenuated to a smaller voltage.

  • So let's go ahead and just do an example here.

  • Let's say for example, we've got the bits of say,

  • we're going to say 1011, that being D3, D2, D1, D0.

  • In the case of a five-volt system, what do we have here

  • for analog output voltage?

  • And you're answer for the combination

  • of 1011 should be 3.4375 volts analog.

  • So again, we should be able to vary this thing.

  • Very similar to our last method of the binary weighted input.

  • We should see a linear relationship developing

  • and in this particular case we got a much smaller solution

  • that our last value.

  • But again, be aware that our range is limited to in this case

  • up to just say of five volts.

  • So the R2R resistance ladder it's simple, effective,

  • accurate, and above all, an inexpensive way

  • to create analog data from digital input.

  • These resistive networks, you know,

  • they're sometimes monolithic, they can be produced en masse

  • in monolithic, a single layer or single piece.

  • They are semiconductor devices

  • that can easily be manufactured over and over.

  • And again, you just go ahead and expand that out

  • if you continuously want to add more to this.

  • You know, for example, a phi bit network,

  • D0 would be D0 divided by 32.

  • D1, divided by 16.

  • D2, divided by 8.

  • D3, divided by 4.

  • D4, divided by 2.

  • So you can potentially expand these networks.

  • This concludes the R2R Resistive Ladder Network

  • for Digital Analog Conversion.

>> Jim Pytel: Good day.

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DACメソッド R2Rラダー (DAC Methods R2R Ladder)

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    jmkuoa に公開 2021 年 01 月 14 日
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