you know designing a circuits for low power has become so much very important in the present

day scenario and it also affects the way vlsi chips are designed and also in particular

the physical design process the so called back end design of the vlsi chips the way

they are done today some techniques and some rules you can say design rules are incorporated

at various stages of the design so that out final product the chip consumes less power

ok so that is the topic of our discussion today

low power vlsi design so as i said power consumption is ah very big challenge perhaps the most

important challenge in modern day vlsi design which is pushing performance to a secondary

level the primary reason is that almost all the devices we use today they are portable

in nature other then of course the desktops which sit on our tables this portable devices

all run on battery power ok you think of our mobile phones our laptops our notebooks our

tabs everything these are the devices which we use they all get the energy from the battery

that is built inside it so if you can design the circuits that get

embedded into these devices in a way that they consume less power or energy whatever

you call so the battery life of the devices tend to increase which is extremely desirable

from the users prospective ok so there have been various works and strategies that have

been proposed over the years which try to reduce the power dissipation so we sometime

say that we have added a fourth dimension to the design process what are the other three

dimensions lets see you see this is a typical picture that will find in several places in

some textbooks also traditionally in this seventies and eighties area and delay were

the most important parameters so when someone try to design a circuit a

chip the primary emphasis was how much less area is occupied by my circuits on the chip

on the silicon floor and what is the maximum speed so we try to reduce the delay [vocalized-noise]

now often this area and delay are mutually conflicting so some typical figure of merits

were ah proposed and used one of them was the product of area and delay square a d square

so there there there are number of such have a matrix which you are used and proposed so

you can have a figure of merit but as the circuits started to become more

and more complex so what happened was that you see area and delay were not the only parameters

now after a chip is manufactured mean one very important task of the designers or you

can say the text engineers was to ensure that the chip does not contain any apparent fabrication

defects so the chip needs to go through a process of testing more the complexity increases

in a chip the task of the testing becomes more and more difficult

so there has to be some design rules like the design for testibility techniques that

where discussed earlier those have to be incorporated or embedded in the design process itself so

that whatever circuits we design they are easily testable so thats why we say that in

the eighties and nineties this third axis of this in this diagram testability came into

the picture but now two thousand onwards with the advent of battery operated mobile devices

portable devices power as become a very important fourth parameter in this design space

so not only we have to address area delay and testability also you have to address this

power consumption issue ok fine so let us look at some of the terminologies so in a

typical chip which in todays technology is normally built using c mos technology so we

say that power is dissipated whenever there is a current flowing from the power supply

which you called the v dd to the ground so power is drawn from the voltage source and

this source i mean sources of these currents can be various these we shall be seeing subsequently

but let us look at how we typically measure the power so i shall be explaining this very

clearly so we distinguish between instantaneous power energy and average power so how are

they defined see instantaneous power is defined simple by the product of the current and the

voltage the current flowing from v dd to ground we call it as i dd this is a function of time

t multiplied by the voltage v dd now instantaneous power does not give us a very clear picture

of means how much our battery is getting drain because it may so happen that sometimes the

instantaneous power is very high but over long period of time we are consuming very

low power means our currents is very less ok

so some sort of average is more meaningful instead of the power drawn at a particular

point in time ok so we talk about energy so how is the energy defined so i shall be explaining

these terminologies graphically very shortly this energy is defined as the integral of

the instantaneous power over a period of time let say capital t zero to t what is the sum

of the instantaneous power drawn that aggregation is defined as the energy this is how you define

ok and of course you are computing this energy over a time period t so if you calculate the

average simply divide this e by t you get the average power

so normally when we evaluate the power consumption of a circuit or a device or a chip we talk

about the energy or the average power now let us see with the help of a diagram how

these three things are related so let us show a typical diagram this is the access of time

and here we show the instantaneous power consumption which means the the product of the current

and the voltage lets say we [vocalized-noise] the value of p t varies with time like this

lets say so we are interested to measure the power between time zero and capital t

now just recalling the definitions for a particular value of t lets say here so if we try to see

what is the corresponding value of p t it is here this is the value of the instantaneous

power i p instantaneous power at this particular time lets say t i right now if i want to calculate

the energy so energy as i said is the integral of pt from zero to capital t so so what is

the physical interpretation of the integral integral means the area under this curve so

this total area under the curve this is defined as the energy that is integral pt dt between

zero and t now if you just take the average energy over

this time p t [vocalized-noise] it is energy is varying so possible the average will be

somewhere here you show it as a straight line so this will give you the average power p

avg now as i said p average can be computed by dividing the energy divide with this time

t so we understand this p average is this level that means the height of this rectangle

and energy is the total area height multiplied by the width and width is capital t

so if we divide this area by capital t you will be getting this height that means p average

ok so diagrammatically i am showing you the difference between instantaneous power the

energy and the average power ok so let us come back so talking about [vocalized-noise]

power dissipation in a typical c mos circuit we can classify the power dissipation into

three types very broadly dynamic short circuit and static so we shall see what are the sources

of these different kinds of powers and what are the typical methods that are adopted to

reduce the effects of these ok so we shall see this subsequently let us start

with dynamic power well [vocalized-noise] as the name implies dynamic power is something

which is depending on the dynamics of the circuits what is the definition of dynamics

something which changes with time so dynamics power by its definition means whenever some

signals in the circuits are changing those changes cause some dissipation of power that

is basically what is meant by dynamics power dissipation so lets try to understand this

so basically dynamics power is required for what purpose for charging and discharging

load capacitances with transistor switch so let us look at very simple example of a

c mos inverter so here i have a p mos transistor and n mos

transistor this is my input let say a and this is my output lets say f so f is given

by the complement of a and this is v dd now what i am saying is that this output as i

said earlier may be driving the inputs of other gates so we can equivalently assume

that it is driving a load capacitance lets say the load capacitance is c so lets say

when the value of a switches from zero to one lets say the value of f will be switching

from one to zero similarly when a switches back to zero the

value of f will again switch to one now whenever this output node f changes from high to low

and low to high what does this mean whenever it is changing from high to low this means

c is getting discharged and whenever it is rising from low to high we say c is getting

charged ok now in this circuits the discharging path of the capacitor is this through the

pull down transistor and the charging path of the capacitor is this through the pull

up transistor so as you know in a c mos circuit depending

on the value of a so either the pull up or the pull down one of the networks is conducting

so depending on that this c will be either discharging or it will be charging now every

time there is a charging discharging of a capacitor it will consume ah power because

you recall the basic definition from circuit theory current is defined as c dv d t so you

can define the current flowing as the product of the capacitor and the rate of change of

voltage so whenever there is a this kind of charging

discharging going on there will be a current flowing and the product of currents and voltage

will be the power consumption ok fine so let us come back to this slide [vocalized-noise]

so i have ah just shown in one cycle we can have a rising output and also falling output

right so whenever there is a rising output that means the output node is getting charged

charge means what the capacitor is getting charge to v dd so what is the total charge

charge is the product of capacitance and voltage so c multiplied by v dd this much charge is

required to charge the output node to v dd similarly when the output goes to zero the

load capacitor needs to discharge to ground right now it can so happen that lets say we

are considering a certain time period t right now within this time period t the output f

may be going up and going down several times this may so happen depending on the behavior

of the circuit now if this kind of thing happens which means in the same interval of time t

the capacitor is getting charged and discharged multiple number of times see charging discharging

charging discharging charging discharging ok

so if i define a parameter f sw this is the frequency of switching then within a time

period t so if you multiple t with f sw this will be number of switching that is taking

place within this time period t the product of the time and the frequency of switching

this you can call as the frequency of switching sw right fine so this already i have ah explained

that if the frequency of output switching is f sw that charging and discharging cycle

will be repeating so many times over a time interval t ok

now let us see that how we can calculate the average dynamic power in a circuit now our

assumption is that we have a circuit like this where there is a period time t and the

inputs are changing at some rate so i am again showing that picture that i am concentrating

my calculation within a time period of t and within the time period t the input or the

output [vocalized-noise] whatever we call in inverter both will be the same will be

changing certain number of times so i am calling it as the frequency of switch right fine

now let us look at this calculation so how do we calculate the dynamic power this is

actually the average power consumption so whenever the output ah is switching so between

time zero and t i simple multiple the current with the voltages this is the definition of

the instantaneous power you integrate it over a time t you get the energy take the average

you get the average power ok since v dd is a constant you take it out so you have an

expression like this so let us see how from here i get this so we get an expression like

this i am just to working this out so you get v dd divided by t integral zero to t current

d t fine now let us make an observation so our observation

is the value of current is defined as the product of the capacitance and the rate of

change of voltage so if you take this into account so i dd tdt becomes c dv so i can

write it as v dd by t integral c dv now the independent variable is v so what will be

the range of v see i am working from zero to t so this will be from zero to what something

i am writing a question mark here because you see a within this time t as i said charging

and discharging will take place multiple number of times right multiple number of [vocalized-noise]

so far each charging i can say each charging the voltages is going from zero to approximately

v dd in the load capacitor and for discharging it is the reverse v dd back to zero

now in each such cycle i can write it like this v dd by t see c dv is nothing but c into

v now since this charging upto v dd so for every charging it will be c into v dd not

only this how many times it is charging within this period t it is charging if s w multiplied

by t times as i said so f sw multiplied by t this will give you at how many times this

charging and discharging is taking place within this time period t so you will have to multiple

this by this t into f sw this will give you the total value of the integrate see here

basically this integral you are separating out between these each of these segments one

two three so thats why if you just add them out there are so many such segments you multiple

this by this right so how much this comes to if you make a simplification

c v dd square capital t cancels out and f sw this is the final expression for dynamics

power right ok so in this expression also this same thing is shown finally the value

of the dynamics power is this and the point to observe here is that the dynamics power

is proportional to load capacitance so to reduce it you can try and reduce the value

of c proportional to square of v dd so if it is possible to reduce the supply voltage

that will also be good and of course proportional to the signal switching frequency

so if you can reduce the frequency that will also result in less dynamics power ok now

taking the concept of dynamic power one step forward let us define something called an

activity factor now see in the previous expression we talked about this f sw which was the frequency

of switching of the input or the output signals right now here we are talking about the clock

frequency f is our clock frequency now we are trying to relate this f sw with f by multiplying

it with the parameter alpha which is defined as the activity factor

you see some signal can change state at a rate which is at most equal to the clock frequency

because it is the clock the edges of the clock that defines the various events in a circuits

but all edges of the clock need not result in a change in the signal state so only a

fraction of the clock edges will actually result in an activity that will result in

consumption of dynamics power so we define something called an activity factor which

if we multiplied by the frequency we get f sw this is how we just estimate f sw now if

you are directly connecting the clock with the gate input so the input as well as the

output will be changing at every edge of the clock

so there we say alpha equal to one but if the gate output switches once per clock cycles